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Silicon Labs /Series0 /EZR32HG /EZR32HG220F32R63 /USARTRF1 /IFC

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Interpret as IFC

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TXC)TXC 0 (RXFULL)RXFULL 0 (RXOF)RXOF 0 (RXUF)RXUF 0 (TXOF)TXOF 0 (TXUF)TXUF 0 (PERR)PERR 0 (FERR)FERR 0 (MPAF)MPAF 0 (SSM)SSM 0 (CCF)CCF

Description

Interrupt Flag Clear Register

Fields

TXC

Clear TX Complete Interrupt Flag
RXFULL

Clear RX Buffer Full Interrupt Flag
RXOF

Clear RX Overflow Interrupt Flag
RXUF

Clear RX Underflow Interrupt Flag
TXOF

Clear TX Overflow Interrupt Flag
TXUF

Clear TX Underflow Interrupt Flag
PERR

Clear Parity Error Interrupt Flag
FERR

Clear Framing Error Interrupt Flag
MPAF

Clear Multi-Processor Address Frame Interrupt Flag
SSM

Clear Slave-Select In Master Mode Interrupt Flag
CCF

Clear Collision Check Fail Interrupt Flag

Links

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Register License

  • SPDX-License-Identifier: Zlib
  • The licensor of this software is Silicon Laboratories Inc.
  • This software is provided ‘as-is’, without any express or implied
  • warranty. In no event will the authors be held liable for any damages
  • arising from the use of this software.
  • Permission is granted to anyone to use this software for any purpose,
  • including commercial applications, and to alter it and redistribute it
  • freely, subject to the following restrictions:
    1. The origin of this software must not be misrepresented; you must not
  • claim that you wrote the original software. If you use this software
  • in a product, an acknowledgment in the product documentation would be
  • appreciated but is not required.
    1. Altered source versions must be plainly marked as such, and must not be
  • misrepresented as being the original software.
    1. This notice may not be removed or altered from any source distribution.
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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data